Verification Leader TransEDA Launches VN-Property DX Dynamic Property Checker
Newest Component of Verification Navigator Environment Speeds Complex System Verification
LOS GATOS, Calif.--(BUSINESS WIRE)--March 4, 2002--TransEDA®,
the leader in ready-to-use verification solutions for electronic
designs, today introduced VN-Property DX(TM), a dynamic property
checker that verifies properties during system simulation. It
accelerates verification of complex systems by measuring the
effectiveness of simulation against design-specific properties.
VN-Property DX is the newest addition to the company's
Verification Navigator® integrated design verification environment,
which gives a unified view of verification completeness for complex
system-on-chip (SoC), application-specific integrated circuit (ASIC),
and field-programmable gate array (FPGA) designs. The new product
enables engineers to answer the question, "Is my design fully
verified?" by determining if specific verification requirements have
been satisfied during simulation. It also provides property coverage
as a metric to direct the verification effort and determine when to
stop.
VN-Property DX enables property checking during any simulation,
independent of the test generation approach used. This enables
engineers to preserve investments in existing infrastructure.
VN-Property DX also allows complex properties to be checked at the
system level, eliminating the state explosion problem found with
formal verification tools.
"TransEDA's VN-Property DX is the first in a planned series of
tools that use properties to unite formal verification with
simulation, as well as block-level with system-level verification,"
said Tom Borgstrom, vice president of marketing at TransEDA. "The
product enables engineers to comprehensively, independently, and
objectively confirm that they've fully verified the behavior of their
designs. Together with code and finite state machine (FSM) coverage
analysis, dynamic property checking provides a powerful means to
improve the efficiency and speed the closure of the verification
process."
Bridging the Gap Between Formal Verification and Simulation
"VN-Property DX represents an innovative new vision for design
verification, helping to bridge the gap between formal verification
and simulation," said Thomas W. Albrecht, director, Chips, Electronics
& Software Design Services at Program and System Engineering, Siemens
Austria. "We found that it was much easier to develop properties in
Perl than it was to write equivalent checkers in VHDL. TransEDA's
pre-defined property libraries for standard interfaces like PCI make
property development even faster."
A Ready-to-Use Solution for Assuring Complete Verification
VN-Property DX enables arbitrarily complex design scenarios to be
checked quickly without the need to write complicated HDL checkers or
assertions. Features of VN-Property DX include:
- Dynamic Property Checking: VN-Property DX checks for both
expected and prohibited behavior and allows new properties to
be added and checked, even after simulation. It identifies
violations of properties describing prohibited behavior, and
increases users' confidence in property validity by measuring
the percentage of expected behaviors observed during
simulation.
- Pre-Defined Property Libraries: Engineers can choose
pre-defined, validated property libraries from TransEDA. A PCI
property library is available now; an AMBA AHB/APB property
library will be available in the second quarter of 2002.
Additional property libraries will be released throughout the
year.
- User-Defined Properties: Engineers and IP developers can
create their own properties in industry-standard Perl syntax.
The use of Perl for defining properties enables users who
understand the popular language to start writing properties
without a long learning curve. Properties are HDL-neutral and
independent from design files, facilitating future re-use. In
addition, TransEDA is committed to open industry standards,
and will add support for the industry standard property
language now being defined by Accellera.
- Flexibility: VN-Property DX is ready to use in existing
verification flows, and supports all leading Verilog, VHDL,
and dual-language simulators. The tool works with all test
generation techniques and can serve as an independent check of
verification completeness. It can be used at any stage of the
design integration process, from block level to system level.
Use of Dynamic Property Checking in IP-Based Designs
VN-Property DX enables a new approach for verification of
intellectual property (IP) based designs. Many leading designs consist
of a mix of pre-verified IP cores from both internal and external
sources. This design style introduces new verification challenges such
as validating interface assumptions between blocks and ensuring that
all behaviors, including those specific to external IP cores, have
been simulated and verified. The challenge is compounded by the fact
that the IP user or system integrator often doesn't understand the
detailed behavior of all the cores in the design.
In this verification methodology, IP developers would deliver
properties describing key IP behaviors and interface assumptions. The
IP integrator would then use this collection of properties to ensure
that all critical behaviors were verified during simulation and that
all interface assumptions were confirmed. The IP integrator would then
be able to fully verify the design and quickly track down interface
bugs without having a detailed understanding of each core. Properties
help bridge the gap between IP developer and IP integrator. TransEDA
will work with leading IP developers to facilitate creation and
distribution of properties compatible with VN-Property DX.
"Verified functional quality and fast integration are key points
when talking about integrating of third party IPs into large SoCs,"
said Thomas Hoetzel, COO of sci-worx, a leading IP developer.
"Sci-worx is streamlining its IP verification environment to enable
customers to fully verify the IP's integration and behavior while
speeding up the integration process by looking at the IP as a black
box with a set of functions. TransEDA's VN-Property DX dynamic
property checker is expected to significantly contribute towards such
an integrated SoC verification solution."
About Verification Navigator
TransEDA's Verification Navigator integrated design verification
environment features tools that enable IC designers to manage the
verification process and shorten verification time. In addition to
VN-Property DX, Verification Navigator includes VN-Check(TM)
configurable HDL checker, VN-Cover(TM) coverage analysis,
VN-Optimize(TM) test suite analysis, and VN-Control(TM)
application-specific test automation. Verification Navigator supports
all leading Verilog, VHDL, and dual-language simulators and is
available on the Solaris, HP-UX, AIX, Linux, Windows NT, and Windows
2000 platforms.
Pricing and Availability
VN-Property DX will be released in March 2002 in Verilog, VHDL,
language-neutral, and dual-language configurations. Pricing starts at
$10,000 (U.S.) for a single-language, annual subscription license. The
PCI property library will be released in March 2002; pricing starts at
$10,000 (U.S.) for an annual subscription license. The AMBA AHB/APB
property library will be released in the second quarter of 2002;
pricing starts at $10,000 (U.S.) for an annual subscription license.
For more information on VN-Property DX, visit
www.transeda.com/vnpropertydx.
About TransEDA
TransEDA PLC (symbol TRA on the London Stock Exchange) develops
and markets ready-to-use design verification solutions for electronic
field-programmable gate array (FPGA), application-specific integrated
circuit (ASIC), and system-on-chip (SoC) designs. The company's
verification IP library includes models and properties for advanced
microprocessors and standard bus interfaces.
TransEDA's design verification software performs
application-specific test automation, configurable HDL checking,
dynamic property checking, code and finite state machine (FSM)
coverage analysis, and test suite analysis. TransEDA's tier-one
customers include 18 of the world's top 20 semiconductor vendors.
For more information, visit www.transeda.com or contact TransEDA
at 985 University Avenue, Los Gatos, Calif. 95032 U.S.A., telephone
408/335-1300, fax 408/335-1319, e-mail info@transeda.com.
Note to Editors: TransEDA and Verification Navigator are
registered trademarks and VN-Property DX, VN-Check, VN-Cover, and
VN-Optimize are trademarks of TransEDA. All other trademarks are
properties of their respective holders.
Contact:
TransEDA
North America, Asia, and Japan
Tom Borgstrom, 408/335-1303
tom.borgstrom@transeda.com
or
Armstrong Kendall, Inc.
Jen Bernier, 408/975-9863
jen@akipr.com
or
In the U.K. and Europe:
PentaCom
Sharon Graves, +44 1242 525205
sharon.graves@pentacomagency.com
